1. Field of the Invention
The invention relates to a surface-mounting type semiconductor device comprising a semiconductor chip mounted on a circuit board by an adhesive and sealed with resin and solder bumps disposed on the back surface of the circuit board.
2. Description of the Related Art
Semiconductor devices having a plurality of electrode terminals have been developed and are associated with high-performance electronic circuits. As such a semiconductor device, there is a typically exemplified surface-mounting type package having a plurality of terminals, and the package is known as a plastic ball grid array (hereinafter referred to as PBGA). Since the external terminals of the PBGA can be disposed at the entire back surface of a package, it has a characteristic such that it is suitable for a multi-pin type LSI and has a small packaging area.
An example of a conventional PBGA is explained with reference to FIGS. 8 and 9. FIG. 8 is a sectional view of the PBGA and FIG. 9 is a rear view of the PBGA.
A PBGA 4 is fabricated by forming a die pattern 17 on a front surface of a circuit board 25 on which a semiconductor chip 29 is mounted (hereinafter referred to as front surface), fixing the semiconductor chip 29 onto the die pattern 17 by an adhesive 27, providing a plurality of solder bumps 35 on the back surface of the circuit board 25, and sealing a major portion thereof including the semiconductor chip 29 on the front surface and bonding wires 31, described later, with a sealing resin 33 formed of a thermosetting resin such as in epoxy resin.
The circuit board 25 comprises a resin substrate 11 formed of Bismaleimide Triazine Resin, a copper foil covering the front and back surfaces of the resin substrate 11 that is in the order of 18 .mu.m in thickness, and a copper-plated layer formed on the copper foil, wherein the copper foil and the copper-plated layer are etched to form the die pattern 17 and connection electrodes 19 on the front surface of the resin substrate 11 and a wiring pattern formed on the back surface of the resin substrate 11 and composed of a common wiring pattern 10a and individual wiring patterns 10b.
The die pattern 17 is formed radially on the center of the front surface of the resin substrate 11 and the semiconductor chip 29 is mounted on the die pattern 17 using the adhesive 27, and it serves as a power supply ground of the semiconductor chip 29 and serves to radiate generated heat.
An epoxy conductive adhesive using silver as a filter (additive) is used as the adhesive 27. The conductive adhesive is used for ensuring an electric conduction with an external ground from the back surface of the semiconductor chip 29 through the die pattern 17, through the holes for heat radiation (described later) the common wiring pattern 10a, pad electrodes 21 and the solder bumps 35.
A large number of connection electrodes 19 are formed radially outside the die pattern 17 so as to surround the die pattern 17, and they are connected with respective electrodes of the semiconductor chip 29 by the bonding wires 31. Gold wires each having the diameter of about 0.03 mm and being excellent in electric characteristic and excellent in contact with the connection electrodes 19 are used at the bonding wires 31.
The through-holes 15 for heat radiation are provided on a region where the die pattern 17 of the circuit board 25 is formed. The through-holes 15 are plated with copper at the inner peripheral surfaces for electrically connecting the die pattern 17 and the common wiring pattern 10a situated on the back surface of the circuit board 25 and they serve to radiate heat generated in the semiconductor chip 29.
Through-holes 13 which are plated with copper at the inner peripheral surfaces thereof are also situated at the outer ends of the connection electrodes 19 close to a peripheral edge of the circuit board 25. Each connection electrode 19 on the front surface of the circuit board 25 and each individual wiring pattern 10b on the back surface thereof are electrically connected with one another by these through-holes 13.
As shown in FIG. 9, the common wiring pattern 10a formed on the back surface of the circuit board 25 is formed in various pattern shapes (square in this embodiment) at the center facing the back surface of the semiconductor chip 29 and it extends to an area which has a plurality of solder bumps 35 used for grounding.
A large number of individual wiring patterns 10b are formed at the periphery of the common wiring pattern 10a for individually connecting each through-hole 13 which is formed along each side of the circuit board 25 and each solder bump 35 (excluding nine solder bumps on the common wiring pattern 10a).
Pad electrodes 21 are formed at the positions where the solder bumps 35 are fixed to the common wiring pattern 10a and the individual wiring patterns 10b, and the solder bumps 35 are arranged in line on the pad electrodes. The plurality of solder bumps 35 protrude from the back surface of the PBGA 4 instead of each electrode of the semiconductor chip 29 and serve as connection terminals for electrically connecting with an electrode pattern of a mother board on which the PBGA 4 is mounted. A solder consisting of tin and lead at a mixture ratio of 6 to 4 is used as each solder bump 35.
The PBGA 4 is covered with a protecting resist 23 formed of a modified epoxy resin at the entire surface thereof except a part covered with the sealing resin 33 of the circuit board 25 and a part forming each pad electrode 21 on the back surface of the circuit board 25. FIG. 9 shows the back surface of the PBGA 4 with the protecting resist 23 removed.
Although the PBGA 4 having such a construction has an advantage of high yield because it can be mounted on the surface of a circuit board and can cope with multi-pins without miniaturizing pitches of the solder bumps, and also it can be mounted by the process of a single heating, the PBGA 4 has the following problems in its construction.
The PBGA generally absorbs moisture contained in the ambient atmosphere through the circuit board 25 and the sealing resin 33 shown in FIG. 8 during the storage thereof Accordingly, if the PBGA 4 which absorbed the moisture is heated in a heating furnace to mount the PBGA 4 on the mother board, the moisture absorbed by the PBGA 4 is vaporized and expanded to produce stress. Exfoliation occurs at the interface between the die pattern 17 and the adhesive 27 to generate a gap 28.
The reason why such an exfoliation occurs is described in more detail. The amount of moisture absorbed by the PBGA 4 from the back surface of the circuit board 25 at the side of the solder bumps solder bumps 35 is larger than that from the front surface thereof covered with the sealing resin 33, and particularly the amount of moisture absorbed by the PBGA 4 from the periphery of the common wiring pattern 10a which is smaller than the size of back surface of the semiconductor chip 29 is larger than that from the back surface thereof. The moisture absorbed by the PBGA 4 passes through the protecting resist 23 and the through-holes 15, and it is liable to stay at the portion close to the die pattern 17.
Meanwhile, although the die pattern 17 is plated with gold at the surface thereof for enhancing conductivity relative to the semiconductor chip 29 to be mounted thereon and for preventing corrosion thereof, there is a problem that gold is weak in adhesion with an epoxy resin which is a major component of the adhesive 27 and gold is an inert metal. Accordingly, even if the semiconductor chip 29 is bonded to the die pattern 17 by the adhesive 27, the former is liable to exfoliate from the latter because of the weak adhesion.
Accordingly, when the water built up in the portion close to the die pattern 17 is heated by a heating furnace, and vaporized and expanded to produce stress, the effects thereof appear noticeably on the interface between the die pattern 17 and the adhesive 27, so that exfoliation is liable to occur.
Owing to this exfoliation, the bonding wires 31 which are encircled by the broken lines A, B in FIG. 10 are broken and they are exfoliated from the connection electrodes, causing the problem of degradation of reliability of the semiconductor device.